Effective Dynamic Re-mapping Algorithm for low power Network- on-chip NoC.

Abstract

With the increase in the possibility of incorporating multiple cores on a single chip (MCSoC), the issue of an efficient interconnection that is scalable, takes up small area and has low power consumption must be taken into consideration carefully. Network on chip (NoC) has evolved as a promising solution for efficiently interconnecting multiple core on a single chip (MCSoC). NoC brings conventional networking theories and methods to chip communication and brings notable improvements over the conventional bus systems.

The aim of my research will be to study power consumption in NoC architecture and propose an effective dynamic remapping algorithm to reduce power consumption on NoC. This is done by monitoring the NoC at run time and dynamically re-mapping the cores to reduce power consumption. Low power consumption is desirable in MCSoC because high power increases capacitance, electro magnetic interference (EMI) and dissipates more heat, thereby reducing performance. In addition, must devices built using MCSoC are hand-held devices (battery powered) and therefore might not have access to continuous power supply. I will be using the OASIS NoC which was developed at the Adaptive systems laboratory, the University of Aizu, Graduate School of Computer Science and Engineering. Aizu, Japan to test my Algorithm. OASIS NoC is a complexity effective on-chip interconnection network.