Show simple item record

Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage

dc.date.accessioned2005-12-22T01:35:34Z
dc.date.accessioned2018-11-24T10:24:12Z
dc.date.available2005-12-22T01:35:34Z
dc.date.available2018-11-24T10:24:12Z
dc.date.issued2004-07-12
dc.identifier.urihttp://hdl.handle.net/1721.1/30485
dc.identifier.urihttp://repository.aust.edu.ng/xmlui/handle/1721.1/30485
dc.description.abstractDigital circuits often have a critical path that runs through a smallsubset of the component subblocks, but where the path changes dynamicallyduring operation. Dynamically resizable static CMOS (DRCMOS) logic isproposed as a fine-grain leakage reduction technique that dynamicallydownsizes transistors in inactive subblocks while maintaining speed insubblocks along the current critical path. A 64-entry register free listand a 64-entry pick-two arbiter are used to evaluate DRCMOS. DRCMOS isshown to give a 50% reduction in total power for equal delay in a70 nm technology.
dc.format.extent5 p.
dc.format.extent7595008 bytes
dc.format.extent408267 bytes
dc.language.isoen_US
dc.titleDynamically Resizable Static CMOS Logic for Fine-Grain Leakage


Files in this item

FilesSizeFormatView
MIT-CSAIL-TR-2004-046.pdf408.2Kbapplication/pdfView/Open
MIT-CSAIL-TR-2004-046.ps7.595Mbapplication/postscriptView/Open

This item appears in the following Collection(s)

Show simple item record