| dc.date.accessioned | 2008-04-08T19:28:07Z | |
| dc.date.accessioned | 2018-11-24T10:26:28Z | |
| dc.date.available | 2008-04-08T19:28:07Z | |
| dc.date.available | 2018-11-24T10:26:28Z | |
| dc.date.issued | 1973-12 | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/41087 | |
| dc.identifier.uri | http://repository.aust.edu.ng/xmlui/handle/1721.1/41087 | |
| dc.description | Work reported herein was conducted at the Artificial Intelligence Laboratory, a Massachusetts Institute of Technology research program supported in part by the Advanced Research Projects Agency of the Department of Defense and monitored by the Office of Naval Research under Contract Number N00014-70-A-0362-0005.
Working Papers are informal papers intended for internal use. | en |
| dc.description.abstract | The purpose of this short document is to exhibit how a HACKER-like top-down planning and debugging system can be applied to the problem of the design and debugging of simple analog electronic circuits. I believe, and I hope to establish, that this kind of processing goes on at all levels of the problem-solving process--from specific, concrete applications, like Electronic Design, through abstract piecing together and debugging of problem-solving strategies. | en |
| dc.language.iso | en_US | en |
| dc.publisher | MIT Artificial Intelligence Laboratory | en |
| dc.title | A scenario of Planning and Debugging in Electronic Circuit Design | en |
| dc.type | Working Paper | en |
