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The Assq Chip and Its Progeny

dc.date.accessioned2008-04-15T13:04:35Z
dc.date.accessioned2018-11-24T10:28:45Z
dc.date.available2008-04-15T13:04:35Z
dc.date.available2018-11-24T10:28:45Z
dc.date.issued1982-01
dc.identifier.urihttp://hdl.handle.net/1721.1/41168
dc.identifier.urihttp://repository.aust.edu.ng/xmlui/handle/1721.1/41168
dc.description.abstractThe Assq Chip lives on the memory bus of the Scheme-81 chip of Sussman et al and serves as a utility for the computation of a number of functions concerned with the maintenance of linear tables and lists. Motivated by a desire to apply the design methodology implicit in Scheme-81, it was designed in about two months, has a very simple architecture and layout, and is primarily machine-generated. The chip and the design process are described and evaluated in the context of a proposal to construct a Scheme-to-silicon compiler that automates the design methodology used in the Assq Chip.en
dc.language.isoen_USen
dc.publisherMIT Artificial Intelligence Laboratoryen
dc.titleThe Assq Chip and Its Progenyen
dc.typeWorking Paperen


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