| dc.date.accessioned | 2008-04-15T15:05:23Z | |
| dc.date.accessioned | 2018-11-24T10:29:36Z | |
| dc.date.available | 2008-04-15T15:05:23Z | |
| dc.date.available | 2018-11-24T10:29:36Z | |
| dc.date.issued | 1983-01-03 | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/41189 | |
| dc.identifier.uri | http://repository.aust.edu.ng/xmlui/handle/1721.1/41189 | |
| dc.description.abstract | This document describes the three transistor NMOS dynamic ram circuit used in the connection machine. It was designed and implemented by Brewster Kahle, with the assistance of Jim Cherry, Danny Hillis and Tom Knight. Prototypes were fabricated through the APRA MOSIS facility, using both four and three micro design rules. Jim Li and I tested both runs this fall. They work. This document describes how. | en |
| dc.language.iso | en_US | en |
| dc.publisher | MIT Artificial Intelligence Laboratory | en |
| dc.title | The Connection Machine RAM Chip | en |
| dc.type | Working Paper | en |
