A Method for Skew-free Distribution of Digital Signals Using Matched Variable Delay Lines
dc.date.accessioned | 2004-10-04T14:25:28Z | |
dc.date.accessioned | 2018-11-24T10:11:24Z | |
dc.date.available | 2004-10-04T14:25:28Z | |
dc.date.available | 2018-11-24T10:11:24Z | |
dc.date.issued | 1992-03-01 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/5986 | |
dc.identifier.uri | http://repository.aust.edu.ng/xmlui/handle/1721.1/5986 | |
dc.description.abstract | The ability to distribute signals everywhere in a circuit with controlled and known delays is essential in large, high-speed digital systems. We present a technique by which a signal driver can adjust the arrival time of the signal at the end of the wire using a pair of matched variable delay lines. We show an implemention of this idea requiring no extra wiring, and how it can be extended to distribute signals skew-free to receivers along the signal run. We demonstrate how this scheme fits into the boundary scan logic of a VLSI chip. | en_US |
dc.format.extent | 13 p. | en_US |
dc.format.extent | 36138 bytes | |
dc.format.extent | 144481 bytes | |
dc.language.iso | en_US | |
dc.subject | clock distribution | en_US |
dc.subject | synchronization | en_US |
dc.subject | skew compensation | en_US |
dc.subject | sphase adjustment | en_US |
dc.title | A Method for Skew-free Distribution of Digital Signals Using Matched Variable Delay Lines | en_US |
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