The M-Machine Multicomputer
dc.date.accessioned | 2004-10-08T20:35:59Z | |
dc.date.accessioned | 2018-11-24T10:17:45Z | |
dc.date.available | 2004-10-08T20:35:59Z | |
dc.date.available | 2018-11-24T10:17:45Z | |
dc.date.issued | 1995-03-01 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/6636 | |
dc.identifier.uri | http://repository.aust.edu.ng/xmlui/handle/1721.1/6636 | |
dc.description.abstract | The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modern semiconductor technology and the demands of programming systems. The M- Machine computing nodes are connected with a 3-D mesh network; each node is a multithreaded processor incorporating 12 function units, on-chip cache, and local memory. The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine and describes how its mechanisms maximize both single thread performance and overall system throughput. | en_US |
dc.format.extent | 393487 bytes | |
dc.format.extent | 284613 bytes | |
dc.language.iso | en_US | |
dc.title | The M-Machine Multicomputer | en_US |
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