A Coupled Multi-ALU Processing Node for a Highly Parallel Computer
dc.date.accessioned | 2004-10-20T19:57:35Z | |
dc.date.accessioned | 2018-11-24T10:21:57Z | |
dc.date.available | 2004-10-20T19:57:35Z | |
dc.date.available | 2018-11-24T10:21:57Z | |
dc.date.issued | 1992-09-01 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/6807 | |
dc.identifier.uri | http://repository.aust.edu.ng/xmlui/handle/1721.1/6807 | |
dc.description.abstract | This report describes Processor Coupling, a mechanism for controlling multiple ALUs on a single integrated circuit to exploit both instruction-level and inter-thread parallelism. A compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle byscycle basis, and several threads can be active concurrently. Simulation results show that Processor Coupling performs well both on single threaded and multi-threaded applications. The experiments address the effects of memory latencies, function unit latencies, and communication bandwidth between function units. | en_US |
dc.format.extent | 165 p. | en_US |
dc.format.extent | 19986107 bytes | |
dc.format.extent | 16194697 bytes | |
dc.language.iso | en_US | |
dc.subject | runtime scheduling | en_US |
dc.subject | compile time scheduling | en_US |
dc.subject | parallelscomputers | en_US |
dc.subject | multithreading | en_US |
dc.title | A Coupled Multi-ALU Processing Node for a Highly Parallel Computer | en_US |
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