Performance Evaluation of the Scheme 86 and HP Precision Architecture
| dc.date.accessioned | 2004-10-20T20:12:01Z | |
| dc.date.accessioned | 2018-11-24T10:22:43Z | |
| dc.date.available | 2004-10-20T20:12:01Z | |
| dc.date.available | 2018-11-24T10:22:43Z | |
| dc.date.issued | 1989-04-01 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/6978 | |
| dc.identifier.uri | http://repository.aust.edu.ng/xmlui/handle/1721.1/6978 | |
| dc.description.abstract | The Scheme86 and the HP Precision Architectures represent different trends in computer processor design. The former uses wide micro-instructions, parallel hardware, and a low latency memory interface. The latter encourages pipelined implementation and visible interlocks. To compare the merits of these approaches, algorithms frequently encountered in numerical and symbolic computation were hand-coded for each architecture. Timings were done in simulators and the results were evaluated to determine the speed of each design. Based on these measurements, conclusions were drawn as to which aspects of each architecture are suitable for a high- performance computer. | en_US |
| dc.format.extent | 7085809 bytes | |
| dc.format.extent | 2582214 bytes | |
| dc.language.iso | en_US | |
| dc.title | Performance Evaluation of the Scheme 86 and HP Precision Architecture | en_US |
Files in this item
| Files | Size | Format | View |
|---|---|---|---|
| AITR-1103.pdf | 2.582Mb | application/pdf | View/ |
| AITR-1103.ps | 7.085Mb | application/postscript | View/ |