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A Cache Model for Modern Processors

dc.date.accessioned2015-04-10T18:45:07Z
dc.date.accessioned2018-11-26T22:27:23Z
dc.date.available2015-04-10T18:45:07Z
dc.date.available2018-11-26T22:27:23Z
dc.date.issued2015-04-09
dc.identifier.urihttp://hdl.handle.net/1721.1/96525
dc.identifier.urihttp://repository.aust.edu.ng/xmlui/handle/1721.1/96525
dc.description.abstractModern processors use high-performance cache replacement policies that outperform traditional alternatives like least-recently used (LRU). Unfortunately, current cache models use stack distances to predict LRU or its variants, and cannot capture these high-performance policies. Accurate predictions of cache performance enable many optimizations in multicore systems. For example, cache partitioning uses these predictions to divide capacity among applications in order to maximize performance, guarantee quality of service, or achieve other system objectives. Without an accurate model for high-performance replacement policies, these optimizations are unavailable to modern processors. We present a new probabilistic cache model designed for high-performance replacement policies. This model uses absolute reuse distances instead of stack distances, which makes it applicable to arbitrary age-based replacement policies. We thoroughly validate our model on several high-performance policies on synthetic and real benchmarks, where its median error is less than 1%. Finally, we present two case studies showing how to use the model to improve shared and single-stream cache performance.en_US
dc.format.extent15 p.en_US
dc.rightsCreative Commons Attribution 4.0 International*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en_US
dc.titleA Cache Model for Modern Processorsen_US


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Creative Commons Attribution 4.0 International
Except where otherwise noted, this item's license is described as Creative Commons Attribution 4.0 International