Design and Evaluation of an Adaptive Network on Chip for Multicore Architectures

Abstract

Network – On – Chip (NoC) communication architecture have emerged as a solution to problem of lack of scalability, clock delay, lack of support for concurrent communication and power consumption exhibited by the shared bus communication approach to System - On - Chip (SoC) implementations. However, a NoC communication requirement such as bandwidth is affected by architecture parameters as topology, routing, buffer size etc.

In this project, we implement an adaptive approach of NoC to solve the problems of the static approach method such as routing delay, lack of flexibility and inability to predict dynamic behaviour of the applications. The adaptive approach supports several applications by changing parameters at run – time.