Hardware Emulation Study of Neuronal Processing in Cortex for Pattern Recognition
Artificial Neural network (ANN) is an area of computing that is modeled after the neural network of the biological brain and over the last few decades, has experienced huge success in its application in areas such as business, Medicine, Industry, Automotive, Astronomy, Finance, etc. Since Neural Networks are inherently parallel architectures, there have been several earlier researches to build custom ASIC based systems that include multiple parallel processing units. However, these ASIC based systems suffered from several limitations such as the ability to run only specific algorithms and limitations on the size of a network. Recently, much work has focused on implementing artificial neural networks on reconfigurable computing platforms. Reconfigurable computing allows to increasing the processing density beyond that provided by general-purpose computing systems. Field Programmable Gate Arrays (FPGAs) can be used for reconfigurable computing and offer flexibility in design with performance speeds almost closer to Application Specific Integrated Circuits (ASICs). This thesis presents a study of an FPGA-based acceleration solution and performance exploration of a Feedforward Artificial Neural Networks (FFANN). The architecture is described using Very-High-Speed Integrated Circuits Hardware Description Language (VHDL) and implemented and demonstrated on an FPGA board. Synthesis and simulation are made with Quartus II tool and ModelSim respectively. The given system was efficiently trained and evaluated in hardware with digit recognition application.