Performance Evaluation of Queue Processors Vs Risc Architecture
Nowadays, shifts in Hardware and Software technologies have forced designers and users to look at micro-architecture that process instructions stream with high performance and low power consumption. In Striving for such high performance, the Queue Processor has been designed with architecture which has the following features: Low power consumption Smaller code size Simple Hardware High Performance in terms of Speed High Instruction level parallelism This research aims at comparing and evaluating these performance features of the Queue Processor architecture with the traditionally used RISC architecture. Evaluation will be done in terms of Software (code size, execution time) and Hardware (Logical Elements, power and speed). This evaluation is performed using Quartus II IDE by Altera. The QSoC will be used as case study for the Queue Processor while Aquarius will be used as case study for the RISC processor. I’m confident that this evaluation research will show a significant improvement in the performance of the Queue Processor over the RISC Architecture.